Name: Introduction to FPGA Programming
Start: 2024-08-26T09:00:00+02:00
End: 2024-08-30T15:00:00+02:00
Location: New

Monday, 26 August 2024
09:00 Lesson 1: Digital Systems, FPGAs and HDL - Davide Cieri (Max-Planck-Institut für Physik )
Lesson 1: Digital Systems, FPGAs and HDL
- Davide Cieri (Max-Planck-Institut für Physik )
09:00 - 09:45
Room: A.1.01/03 - Alps
09:45 Lab 1: First Look at Vivado
Lab 1: First Look at Vivado
09:45 - 10:05
Room: A.1.01/03 - Alps

10:05 Lab 2: Simulating an HDL design with Vivado and GHDL
Lab 2: Simulating an HDL design with Vivado and GHDL
10:05 - 11:00
Room: A.1.01/03 - Alps

11:00 Coffee break
Coffee break
11:00 - 11:30
Room: A.1.01/03 - Alps
11:30 Lesson 2: VHDL Fundamentals - Davide Cieri (Max-Planck-Institut für Physik )
Lesson 2: VHDL Fundamentals
- Davide Cieri (Max-Planck-Institut für Physik )
11:30 - 12:00
Room: A.1.01/03 - Alps
12:00 Lab 3: Wiring Switches to LEDs
Lab 3: Wiring Switches to LEDs
12:00 - 12:30
Room: A.1.01/03 - Alps
Tuesday, 27 August 2024
09:00 Lesson 3: Boolean Algebra, Look-up Tables and IOs - Davide Cieri (Max-Planck-Institut für Physik )
Lesson 3: Boolean Algebra, Look-up Tables and IOs
- Davide Cieri (Max-Planck-Institut für Physik )
09:00 - 09:30
Room: A.1.01/03 - Alps
09:30 Lab 4: Wiring Switches to LED (part II)
Lab 4: Wiring Switches to LED (part II)
09:30 - 10:00
Room: A.1.01/03 - Alps

10:00 Lab 5: Implement a Full Adder
Lab 5: Implement a Full Adder
10:00 - 10:20
Room: A.1.01/03 - Alps

10:20 Lab 6: Hierarchical Design
Lab 6: Hierarchical Design
10:20 - 11:00
Room: A.1.01/03 - Alps

11:00 Coffee Break
Coffee Break
11:00 - 11:30
Room: A.1.01/03 - Alps

11:30 Lesson 4: Sequential Logic and Flip-Flops
Lesson 4: Sequential Logic and Flip-Flops
11:30 - 12:00
Room: A.1.01/03 - Alps

12:00 Lab 7: Counters and Debouncing
Lab 7: Counters and Debouncing
12:00 - 12:30
Room: A.1.01/03 - Alps

12:30 Lab 8: An LED Blinker
Lab 8: An LED Blinker
12:30 - 13:00
Room: A.1.01/03 - Alps
Wednesday, 28 August 2024
09:00 Lesson 5: Types, Arrays and Arithmetic Functions - Davide Cieri (Max-Planck-Institut für Physik )
Lesson 5: Types, Arrays and Arithmetic Functions
- Davide Cieri (Max-Planck-Institut für Physik )
09:00 - 09:30
Room: A.1.01/03 - Alps
09:30 Lab 9: Design an Arithmetic Logic Unit
Lab 9: Design an Arithmetic Logic Unit
09:30 - 10:30
Room: A.1.01/03 - Alps

10:30 Coffee Break
Coffee Break
10:30 - 11:00
Room: A.1.01/03 - Alps

11:00 Lesson 6: VHDL Simulation
Lesson 6: VHDL Simulation
11:00 - 11:40
Room: A.1.01/03 - Alps

11:40 Lab 10: Testbench Coding
Lab 10: Testbench Coding
11:40 - 12:40
Room: A.1.01/03 - Alps
Thursday, 29 August 2024

09:00 Lesson 7: Storing Data on FPGAs
Lesson 7: Storing Data on FPGAs
09:00 - 09:30
Room: A.1.01/03 - Alps

09:30 Lab 11: Trigonometric Functions on FPGA
Lab 11: Trigonometric Functions on FPGA
09:30 - 10:15
Room: A.1.01/03 - Alps

10:15 Coffee Break
Coffee Break
10:15 - 10:35
Room: A.1.01/03 - Alps

10:35 Lesson 8: Packages, Libraries and Parametrisation
Lesson 8: Packages, Libraries and Parametrisation
10:35 - 11:05
Room: A.1.01/03 - Alps

11:05 Lab 12: Packages and libraries
Lab 12: Packages and libraries
11:05 - 11:35
Room: A.1.01/03 - Alps

11:35 Lab 13: Parameters and Parametised Generation
Lab 13: Parameters and Parametised Generation
11:35 - 12:05
Room: A.1.01/03 - Alps

12:05 Lesson 10: IP Blocks
Lesson 10: IP Blocks
12:05 - 12:25
Room: A.1.01/03 - Alps

12:25 Lab 16: Using IPs
Lab 16: Using IPs
12:25 - 12:45
Room: A.1.01/03 - Alps
Friday, 30 August 2024
09:00 Lesson 9: Finite State Machines - Davide Cieri (Max-Planck-Institut für Physik )
Lesson 9: Finite State Machines
- Davide Cieri (Max-Planck-Institut für Physik )
09:00 - 09:30
Room: A.1.01/03 - Alps
09:30 Lab 14: Improve the Traffic Light
Lab 14: Improve the Traffic Light
09:30 - 10:00
Room: A.1.01/03 - Alps

10:00 Lesson 11: Timing on FPGAs
Lesson 11: Timing on FPGAs
10:00 - 10:40
Room: A.1.01/03 - Alps

10:40 Coffee Break
Coffee Break
10:40 - 11:00
Room: A.1.01/03 - Alps

11:00 Lab 17: Timing Constraints
Lab 17: Timing Constraints
11:00 - 11:20
Room: A.1.01/03 - Alps

11:20 Lab 18: Generating Clocks
Lab 18: Generating Clocks
11:20 - 11:50
Room: A.1.01/03 - Alps

11:50 Lesson 13: External Interfaces
Lesson 13: External Interfaces
11:50 - 12:20
Room: A.1.01/03 - Alps

12:20 Lab 20: UART Transmitter
Lab 20: UART Transmitter
12:20 - 13:00
Room: A.1.01/03 - Alps