Electronics Working Group Results
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Tsingua
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* Single-ch preamp CMOS ASIC, 3x3 mm (could be smaller)
    * Tests of ASIC with high-quality detector(s) in collaboration
	  with Canberra
    * Include differential output in next version
    * Production: Multi-project wafer run, 350 nm process

* Already developing a switched capacitor array (currently for
  GEM readout ASIC)


MPP
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* Collaboration with Tsinhua on multi-channel preamp ASIC tests
* Will contacs IDEAS (Norway) about noise, cryogenic conditions,
  and dynamic range


KIT (M. Kleifges)
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* Long-term interest in low-power digitization for Auger-like
  experiments
* Eureca: Candidate for Ge instrumentation with new technologies
  (e.g. ASIC preamps, switched-capacitor array digitization)


Analog Input Stage Design
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* Investigate analog differentiation in preamp to lower
  dynamic range requirements (calulations by David Radford)