Name: Introduction to FPGA Programming
Start: 2024-08-26T09:00:00+02:00
End: 2024-08-30T15:00:00+02:00
Location: MPP

Introduction to FPGA Programming

from Monday, August 26, 2024 (9:00 AM) to Friday, August 30, 2024 (3:00 PM)

Monday, August 26, 2024
9:00 AM Lesson 1: Digital Systems, FPGAs and HDL - Davide Cieri (Max-Planck-Institut für Physik )
Lesson 1: Digital Systems, FPGAs and HDL
- Davide Cieri (Max-Planck-Institut für Physik )
9:00 AM - 9:45 AM
Room: A.1.01 - Alps Süd
9:45 AM Lab 1: First Look at Vivado
Lab 1: First Look at Vivado
9:45 AM - 10:05 AM
Room: A.1.01 - Alps Süd

10:05 AM Lab 2: Simulating an HDL design with Vivado and GHDL
Lab 2: Simulating an HDL design with Vivado and GHDL
10:05 AM - 11:00 AM
Room: A.1.01 - Alps Süd

11:00 AM Coffee break
Coffee break
11:00 AM - 11:30 AM
Room: A.1.01 - Alps Süd
11:30 AM Lesson 2: VHDL Fundamentals - Davide Cieri (Max-Planck-Institut für Physik )
Lesson 2: VHDL Fundamentals
- Davide Cieri (Max-Planck-Institut für Physik )
11:30 AM - 12:00 PM
Room: A.1.01 - Alps Süd
12:00 PM Lab 3: Wiring Switches to LEDs
Lab 3: Wiring Switches to LEDs
12:00 PM - 12:30 PM
Room: A.1.01 - Alps Süd
Tuesday, August 27, 2024
9:00 AM Lesson 3: Boolean Algebra, Look-up Tables and IOs - Davide Cieri (Max-Planck-Institut für Physik )
Lesson 3: Boolean Algebra, Look-up Tables and IOs
- Davide Cieri (Max-Planck-Institut für Physik )
9:00 AM - 9:30 AM
Room: A.1.01 - Alps Süd
9:30 AM Lab 4: Wiring Switches to LED (part II)
Lab 4: Wiring Switches to LED (part II)
9:30 AM - 10:00 AM
Room: A.1.01 - Alps Süd

10:00 AM Lab 5: Implement a Full Adder
Lab 5: Implement a Full Adder
10:00 AM - 10:20 AM
Room: A.1.01 - Alps Süd

10:20 AM Lab 6: Hierarchical Design
Lab 6: Hierarchical Design
10:20 AM - 11:00 AM
Room: A.1.01 - Alps Süd

11:00 AM Coffee Break
Coffee Break
11:00 AM - 11:30 AM
Room: A.1.01 - Alps Süd

11:30 AM Lesson 4: Sequential Logic and Flip-Flops
Lesson 4: Sequential Logic and Flip-Flops
11:30 AM - 12:00 PM
Room: A.1.01 - Alps Süd

12:00 PM Lab 7: Counters and Debouncing
Lab 7: Counters and Debouncing
12:00 PM - 12:30 PM
Room: A.1.01 - Alps Süd

12:30 PM Lab 8: An LED Blinker
Lab 8: An LED Blinker
12:30 PM - 1:00 PM
Room: A.1.01 - Alps Süd
Wednesday, August 28, 2024
9:00 AM Lesson 5: Types, Arrays and Arithmetic Functions - Davide Cieri (Max-Planck-Institut für Physik )
Lesson 5: Types, Arrays and Arithmetic Functions
- Davide Cieri (Max-Planck-Institut für Physik )
9:00 AM - 9:30 AM
Room: A.1.01 - Alps Süd
9:30 AM Lab 9: Design an Arithmetic Logic Unit
Lab 9: Design an Arithmetic Logic Unit
9:30 AM - 10:30 AM
Room: A.1.01 - Alps Süd

10:30 AM Coffee Break
Coffee Break
10:30 AM - 11:00 AM
Room: A.1.01 - Alps Süd

11:00 AM Lesson 6: VHDL Simulation
Lesson 6: VHDL Simulation
11:00 AM - 11:40 AM
Room: A.1.01 - Alps Süd

11:40 AM Lab 10: Testbench Coding
Lab 10: Testbench Coding
11:40 AM - 12:40 PM
Room: A.1.01 - Alps Süd
Thursday, August 29, 2024

9:00 AM Lesson 7: Storing Data on FPGAs
Lesson 7: Storing Data on FPGAs
9:00 AM - 9:30 AM
Room: A.1.01 - Alps Süd

9:30 AM Lab 11: Trigonometric Functions on FPGA
Lab 11: Trigonometric Functions on FPGA
9:30 AM - 10:15 AM
Room: A.1.01 - Alps Süd

10:15 AM Coffee Break
Coffee Break
10:15 AM - 10:35 AM
Room: A.1.01 - Alps Süd

10:35 AM Lesson 8: Packages, Libraries and Parametrisation
Lesson 8: Packages, Libraries and Parametrisation
10:35 AM - 11:05 AM
Room: A.1.01 - Alps Süd

11:05 AM Lab 12: Packages and libraries
Lab 12: Packages and libraries
11:05 AM - 11:35 AM
Room: A.1.01 - Alps Süd

11:35 AM Lab 13: Parameters and Parametised Generation
Lab 13: Parameters and Parametised Generation
11:35 AM - 12:05 PM
Room: A.1.01 - Alps Süd

12:05 PM Lesson 10: IP Blocks
Lesson 10: IP Blocks
12:05 PM - 12:25 PM
Room: A.1.01 - Alps Süd

12:25 PM Lab 16: Using IPs
Lab 16: Using IPs
12:25 PM - 12:45 PM
Room: A.1.01 - Alps Süd
Friday, August 30, 2024
9:00 AM Lesson 9: Finite State Machines - Davide Cieri (Max-Planck-Institut für Physik )
Lesson 9: Finite State Machines
- Davide Cieri (Max-Planck-Institut für Physik )
9:00 AM - 9:30 AM
Room: A.1.01 - Alps Süd
9:30 AM Lab 14: Improve the Traffic Light
Lab 14: Improve the Traffic Light
9:30 AM - 10:00 AM
Room: A.1.01 - Alps Süd

10:00 AM Lesson 11: Timing on FPGAs
Lesson 11: Timing on FPGAs
10:00 AM - 10:40 AM
Room: A.1.01 - Alps Süd

10:40 AM Coffee Break
Coffee Break
10:40 AM - 11:00 AM
Room: A.1.01 - Alps Süd

11:00 AM Lab 17: Timing Constraints
Lab 17: Timing Constraints
11:00 AM - 11:20 AM
Room: A.1.01 - Alps Süd

11:20 AM Lab 18: Generating Clocks
Lab 18: Generating Clocks
11:20 AM - 11:50 AM
Room: A.1.01 - Alps Süd

11:50 AM Lesson 13: External Interfaces
Lesson 13: External Interfaces
11:50 AM - 12:20 PM
Room: A.1.01 - Alps Süd

12:20 PM Lab 20: UART Transmitter
Lab 20: UART Transmitter
12:20 PM - 1:00 PM
Room: A.1.01 - Alps Süd

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