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Introduction to FPGA Programming

2–13 Sept 2024
MPP
Europe/Berlin timezone

Contribution List

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  1. 1. Lesson 1: Digital Systems, FPGAs and HDL
    Davide Cieri (Max-Planck-Institut für Physik )
    02/09/2024, 09:00
  2. 2. Lab 1: First Look at Vivado
    02/09/2024, 09:45
  3. 3. Lab 2: Simulating an HDL design with Vivado and GHDL
    02/09/2024, 10:05
  4. 4. Lesson 2: VHDL Fundamentals
    Davide Cieri (Max-Planck-Institut für Physik )
    02/09/2024, 11:30
  5. 5. Lab 3: Wiring Switches to LEDs
    02/09/2024, 12:00
  6. 6. Lesson 3: Boolean Algebra, Look-up Tables and IOs
    Davide Cieri (Max-Planck-Institut für Physik )
    03/09/2024, 09:00
  7. 7. Lab 4: Wiring Switches to LED (part II)
    03/09/2024, 09:30
  8. 8. Lab 5: Implement a Full Adder
    03/09/2024, 10:00
  9. 9. Lab 6: Hierarchical Design
    03/09/2024, 10:20
  10. 10. Lesson 4: Sequential Logic and Flip-Flops
    03/09/2024, 11:30
  11. 11. Lab 7: Counters and Debouncing
    03/09/2024, 12:00
  12. 12. Lab 8: An LED Blinker
    03/09/2024, 12:30
  13. 13. Lesson 5: Types, Arrays and Arithmetic Functions
    Davide Cieri (Max-Planck-Institut für Physik )
    04/09/2024, 09:00
  14. 14. Lab 9: Design an Arithmetic Logic Unit
    04/09/2024, 09:30
  15. 15. Lesson 6: VHDL Simulation
    04/09/2024, 11:00
  16. 16. Lab 10: Testbench Coding
    04/09/2024, 11:40
  17. 17. Lesson 7: Storing Data on FPGAs
    05/09/2024, 09:00
  18. 18. Lab 11: Trigonometric Functions on FPGA
    05/09/2024, 09:30
  19. 19. Lesson 8: Packages, Libraries and Parametrisation
    05/09/2024, 11:00
  20. 20. Lab 12: Packages and libraries
    05/09/2024, 11:30
  21. 21. Lab 13: Parameters and Parametised Generation
    05/09/2024, 12:00
  22. 22. Lesson 9: Finite State Machines
    Davide Cieri (Max-Planck-Institut für Physik )
    06/09/2024, 09:00
  23. 23. Lab 14: Improve the Traffic Light
    06/09/2024, 09:30
  24. 31. Lesson 9a: The 7-segment Display
    06/09/2024, 10:00
  25. 32. Lab 15: Design a Stopwatch
    06/09/2024, 10:50
  26. 24. Lesson 10: IP Blocks
    09/09/2024, 09:00
  27. 25. Lab 16: Using IPs
    09/09/2024, 09:30
  28. 26. Lesson 11: Timing on FPGAs
    09/09/2024, 10:00
  29. 27. Lab 17: Timing Constraints
    09/09/2024, 11:15
  30. 28. Lab 18: Generating Clocks
    09/09/2024, 11:45
  31. 33. Lesson 12: Hardware Debugging
    10/09/2024, 09:00
  32. 34. Lab 19: Hardware Debugging
    10/09/2024, 09:30
  33. 36. Lesson 14: Advanced Vivado Flow
    10/09/2024, 11:00
  34. 37. Lab 22: Advanced Vivado Flow
    10/09/2024, 11:30
  35. 29. Lesson 13: External Interfaces
    11/09/2024, 09:00
  36. 30. Lab 20: UART Transmitter
    11/09/2024, 09:30
  37. 43. Lesson 13a: VGA Screens
    11/09/2024, 11:00
  38. 35. Lab 21. Connect to the VGA Display
    11/09/2024, 11:30
  39. 40. Lesson 15: Processors on FPGA
    12/09/2024, 09:00
  40. 41. Lab 23: Implementing a Microblaze soft processor
    12/09/2024, 09:30
  41. 42. Lesson 16: Advanced FPGA topics
    12/09/2024, 11:00
  42. 44. Course Examination
    13/09/2024, 09:00
  43. 39. Lab 23: Design Management
  44. 38. Lesson 15: Design Management with Vivado