Login

Introduction to FPGA Programming

Sep 2 – 13, 2024
MPP
Europe/Berlin timezone

Contribution List

44 out of 44 displayed
Export to PDF
  1. 1. Lesson 1: Digital Systems, FPGAs and HDL
    Davide Cieri (Max-Planck-Institut für Physik )
    9/2/24, 9:00 AM
  2. 2. Lab 1: First Look at Vivado
    9/2/24, 9:45 AM
  3. 3. Lab 2: Simulating an HDL design with Vivado and GHDL
    9/2/24, 10:05 AM
  4. 4. Lesson 2: VHDL Fundamentals
    Davide Cieri (Max-Planck-Institut für Physik )
    9/2/24, 11:30 AM
  5. 5. Lab 3: Wiring Switches to LEDs
    9/2/24, 12:00 PM
  6. 6. Lesson 3: Boolean Algebra, Look-up Tables and IOs
    Davide Cieri (Max-Planck-Institut für Physik )
    9/3/24, 9:00 AM
  7. 7. Lab 4: Wiring Switches to LED (part II)
    9/3/24, 9:30 AM
  8. 8. Lab 5: Implement a Full Adder
    9/3/24, 10:00 AM
  9. 9. Lab 6: Hierarchical Design
    9/3/24, 10:20 AM
  10. 10. Lesson 4: Sequential Logic and Flip-Flops
    9/3/24, 11:30 AM
  11. 11. Lab 7: Counters and Debouncing
    9/3/24, 12:00 PM
  12. 12. Lab 8: An LED Blinker
    9/3/24, 12:30 PM
  13. 13. Lesson 5: Types, Arrays and Arithmetic Functions
    Davide Cieri (Max-Planck-Institut für Physik )
    9/4/24, 9:00 AM
  14. 14. Lab 9: Design an Arithmetic Logic Unit
    9/4/24, 9:30 AM
  15. 15. Lesson 6: VHDL Simulation
    9/4/24, 11:00 AM
  16. 16. Lab 10: Testbench Coding
    9/4/24, 11:40 AM
  17. 17. Lesson 7: Storing Data on FPGAs
    9/5/24, 9:00 AM
  18. 18. Lab 11: Trigonometric Functions on FPGA
    9/5/24, 9:30 AM
  19. 19. Lesson 8: Packages, Libraries and Parametrisation
    9/5/24, 11:00 AM
  20. 20. Lab 12: Packages and libraries
    9/5/24, 11:30 AM
  21. 21. Lab 13: Parameters and Parametised Generation
    9/5/24, 12:00 PM
  22. 22. Lesson 9: Finite State Machines
    Davide Cieri (Max-Planck-Institut für Physik )
    9/6/24, 9:00 AM
  23. 23. Lab 14: Improve the Traffic Light
    9/6/24, 9:30 AM
  24. 31. Lesson 9a: The 7-segment Display
    9/6/24, 10:00 AM
  25. 32. Lab 15: Design a Stopwatch
    9/6/24, 10:50 AM
  26. 24. Lesson 10: IP Blocks
    9/9/24, 9:00 AM
  27. 25. Lab 16: Using IPs
    9/9/24, 9:30 AM
  28. 26. Lesson 11: Timing on FPGAs
    9/9/24, 10:00 AM
  29. 27. Lab 17: Timing Constraints
    9/9/24, 11:15 AM
  30. 28. Lab 18: Generating Clocks
    9/9/24, 11:45 AM
  31. 33. Lesson 12: Hardware Debugging
    9/10/24, 9:00 AM
  32. 34. Lab 19: Hardware Debugging
    9/10/24, 9:30 AM
  33. 36. Lesson 14: Advanced Vivado Flow
    9/10/24, 11:00 AM
  34. 37. Lab 22: Advanced Vivado Flow
    9/10/24, 11:30 AM
  35. 29. Lesson 13: External Interfaces
    9/11/24, 9:00 AM
  36. 30. Lab 20: UART Transmitter
    9/11/24, 9:30 AM
  37. 43. Lesson 13a: VGA Screens
    9/11/24, 11:00 AM
  38. 35. Lab 21. Connect to the VGA Display
    9/11/24, 11:30 AM
  39. 40. Lesson 15: Processors on FPGA
    9/12/24, 9:00 AM
  40. 41. Lab 23: Implementing a Microblaze soft processor
    9/12/24, 9:30 AM
  41. 42. Lesson 16: Advanced FPGA topics
    9/12/24, 11:00 AM
  42. 44. Course Examination
    9/13/24, 9:00 AM
  43. 39. Lab 23: Design Management
  44. 38. Lesson 15: Design Management with Vivado